Embedded VHDL coding for multimode calculator

entity parity is
Port ( se : in STD_LOGIC_VECTOR (2 downto 0);
a : in STD_LOGIC;
b : in STD_LOGIC;
y : out STD_LOGIC);
end parity;

architecture Behavioral of parity is
begin
process (se,a,b)
begin
if (se="000") then y<=a and b;
elsif (se="001") then y<=a or b;
elsif (se="010") then y<=a xor b;
elsif (se="011") then y<= not a;
elsif (se="100") then y<=not b;
elsif (se="111") then y<='0';
end if;
end process;
end Behavioral;