<font color=#AA0000>library IEEE;</font>
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mult1 is
Port ( a,b : in STD_LOGIC_VECTOR (1 downto 0);
s : out STD_LOGIC_VECTOR (3 downto 0));
end mult1;
architecture arraymul of mult1 is
component halfadder1
port(a,b : in STD_LOGIC;
s,c : out STD_LOGIC);
end component;
component and1
port(a,b : in STD_LOGIC;
y : out STD_LOGIC);
end component;
signal x1,x2,x3,c1:STD_LOGIC;
begin
h1:halfadder1 port map(x1,x2,s(1),c1);
h2:halfadder1 port map(c1,x3,s(2),s(3));
z1:and1 port map(a(0),b(0),s(0));
z2:and1 port map(a(1),b(0),x1);
z3:and1 port map(a(0),b(1),x2);
z4:and1 port map(a(1),b(1),x3);
end arraymul;
