VHDL PROGRAM FOR SEQUENTIAL CIRCUITS
library ieee;
use ieee.std_logic_1164.all;
entity jkff is
port(j,k,clk:in bit;q:inout bit);
end jkff;
architecture jkff1 of jkff is
begin
process(clk)
begin
if clk='0'then
if(j=not k)then
q<=j;
elsif(j='0' and k='0')then
q<=q;
elsif(j='1' and k='1')then
q<=not q;
end if;
end if;
end process;
end jkff1;
entity xnor is
port(a,b:in bit;c:out bit);
end xnor;
architecture xnor1 of xnor is
begin
c<=not(a xor b);
end xnor1;
entity and1 is
port(d,e:in bit;f:out bit);
end and1;
architecture and2 of and1 is
begin
f<= d and e;
end and2;
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entity seqckt is
port(j,k:in bit_vector(1 downto 0); e,x,c:in bit;a:inout bit_vector(1 downto 0));
end seqckt;
architecture seqckt1 of seqckt is
component jkff
port(j,k,clk:in bit;q:inout bit);
end component;
component xnor
port(a,b:in bit;c:out bit);
end component;
component and1
port(d,e:in bit;f:out bit);
end component;
signal o1,o2:bit;
begin
sc1:jkff port map(e,e,c,a(0));
sc2:jkff port map(o2,o2,c,a(1));
SC3:xnor port map (a(0),x,o1);
sc4:and1 port map (o1,e,o2);
end seqckt1;
