library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY fourbitcounter IS /* creating an entity for four bit counter */
PORT (
Clock : IN STD_LOGIC;
Enable : IN STD_LOGIC;
Clear_n : IN STD_LOGIC;
Initial_Value : IN STD_LOGIC_VECTOR(3 downto 0);
Load_n : IN STD_LOGIC;
Counter_Output : OUT STD_LOGIC_VECTOR(3 downto 0));
END fourbitcounter;
ENTITY display_driver IS /* creating an entity for seven segment and reset equations */
PORT ( QD, QC, QB, QA : IN STD_LOGIC;
SegA, SegB, SegC, SegD, SegE, SegF, SegG: OUT STD_LOGIC;
Reset_n: OUT STD_LOGIC);
END display_driver;
ENTITY my_counter_display IS
PORT ( Clock : IN STD_LOGIC;
SegA, SegB, SegC, SegD, SegE, SegF, SegG: OUT STD_LOGIC);
END my_counter_display;
ARCHITECTURE structural OF my_counter_display IS
-- Component Declaration
COMPONENT fourbitcounter IS /* New VHDL entity for counter display*/
PORT
( Clock : IN STD_LOGIC;
Enable : IN STD_LOGIC;
Clear_n : IN STD_LOGIC;
Initial_Value : IN STD_LOGIC_VECTOR(3 downto 0);
Load_n : IN STD_LOGIC;
Counter_Output : OUT STD_LOGIC_VECTOR(3 downto 0)
);
END COMPONENT fourbitcounter;
COMPONENT display_driver IS /* Declaring Components */
PORT ( QD, QC, QB, QA : IN STD_LOGIC;
SegA, SegB, SegC, SegD, SegE, SegF, SegG: OUT STD_LOGIC;
Reset_n: OUT STD_LOGIC);
END COMPONENT display_driver;
SIGNAL zero, one  : STD_LOGIC; /* Declaring Signals */
SIGNAL reset_signal  : STD_LOGIC;
SIGNAL init_val  : STD_LOGIC_VECTOR(3 downto 0);
BEGIN – Architecture /* Architecture Body */
zero <= '0';
one <= '1';
init_val <= "0000";
-- Component Instantiation /* Declaring Signals */
the_fourbitcounter: fourbitcounter
PORT MAP (Clock => Clock,
Initial_Value => init_val,
Clear_n => reset_signal,
Enable => one,
Load_n => one,
Counter_Output => four_bit_signal);
