How to initiate the display in VHDL??

Clock : IN STD_LOGIC;
Enable : IN STD_LOGIC;
Clear_n : IN STD_LOGIC;
Initial_Value : IN STD_LOGIC_VECTOR(3 downto 0);
Load_n : IN STD_LOGIC;
Counter_Output : OUT STD_LOGIC_VECTOR(3 downto 0));
END fourbitcounter;

ENTITY display_driver IS /* creating an entity for seven segment and reset equations */
PORT ( QD, QC, QB, QA : IN STD_LOGIC;
SegA, SegB, SegC, SegD, SegE, SegF, SegG: OUT STD_LOGIC;
Reset_n: OUT STD_LOGIC);
END display_driver;